1. Field of the Invention
The present invention generally relates to numerical arithmetic processing apparatus and, more particularly, to a divider suitable for microprocessors.
2. Description of the Prior Art
Conventional dividers have utilized a non-restoring method to divide binary numerical data. The dividers generally include a plurality of registers for storing a divisor, dividend, quotient and other similar values, and a shifter for effecting arithmetic shift.
In the non-restoring method, a quotient is obtained by subtracting a divisor from a dividend and sequentially repeating an arithmetic operation such as computation shift. Assuming that numerical data in a binary notation are divided, a binary number is represented in a numerical format of a fixed point and two's complement, as shown in FIG. 3. Then, a quotient Q is produced by dividing a dividend A by a divisor B, as follows: EQU Q=A/B (1) EQU Given EQU 0.ltoreq.A, 0&lt;B, A&lt;2B (2) EQU then EQU 0.ltoreq.Q&lt;2 (3)
The numerical format of the quotient Q shown in FIG. 3 allocates one bit to a sign position, one bit to an integral part, and N bits to a fractional part.
A procedure for determining the quotient Q as represented by the equation (1) will be described with reference to FIG. 4. Assume that a binary divider divides a dividend A1 by a divisor B1. Then, the procedure depicted in FIG. 4 begins with a step 41 for loading a register Q assigned to a quotient with an initial value which is (logical) ZEROs. Registers A and B are loaded with the dividend A1 and the divisor B1, respectively. The divisor B1 is subtracted from the dividend A1, and the result of subtraction C1 is stored in a register C (step 42). If the result of subtraction C1 is positive as determined in a step 43, a (logical) ONE is stored in the register Q and arithmetically shifted one bit to the left. Let the resulting value in the register Q be C2 (step 44). At the same time, a value C3 produced by doubling the result C1 is written in the register A (step 45).
On the other hand, if the result of subtraction C1 is negative, a ZERO is stored in the register Q and arithmetically shifted one bit to the left in the register Q (step 46). The value so stored in the register Q is assumed to be C4. Further, a value A2 produced by doubling the value A1 is written in the register A (step 47).
The sequence of steps (steps 42 to 47) described above is repeated N+1 times where N is the number of bits allocated to the fractional part (loop 48). Consequently, a quotient Q is stored in the register C.
An ordinary microprocessor lacks an exclusive hardware for executing division as discussed above. Such a microprocessor has a disadvantage that it takes several to several tens of machine cycles per digit of a quotient so that it is difficult to realize a high speed division operation.